Hardware Security Symposium Series: Dr. Paolo Gargini
June 8, 2016

 

Dr. Paolo Gargini, Former Director of Technology Strategy, Intel Corporation and Chairman of the International Technology Roadmap for Semiconductors (ITRS)

Since 1998 Dr. Paolo A. Gargini has served as the chairman of the International Roadmap for Semiconductors, and also heads the International EUV Initiative (IEUVI) and the International Consortia Cooperation Initiative (ICCI). In 2012, Dr. Gargini returned to the world of research after having worked for 34 years at Intel Corporation, where he served as the Director of Technology Strategy in Santa Clara, California. While at Intel, Dr. Gargini was responsible for worldwide research activities conducted by universities and consortia for the benefit of the Technology and Manufacturing Group.

This hardware symposium focused on the development of the microelectronics industry, and where it will be headed in the future. Dr. Gargini separated the development of the microelectronics industry into 3 phases: (1) Geometric Scaling or the Age of Classical Feature Size Scaling: 1975 – 2003; (2) Equivalent Scaling: 2003 – 2020; (3) 3D Architecture: 2020 and beyond. The first phase was defined by Denard scaling, and gate oxide thickness limitations led to the end of this era. Equivalent Scaling has been defined by strained silicon, and high-k metal gate stacks. A key aspect of this density scaling has been that the cost per transistor has been continuously decreasing, yet today we are at an inflection point in which the cost per transistor is now increasing. Logic has not been following Moore's density law for some time, although FLASH memory is still following Moore's law density. The end of Moore’s law will therefore lead to the decline of this age. Lastly, advanced 3D architectures, including staking and advanced packing, are likely to define the future of the microelectronics industry. The International Technology Roadmap for Semiconductors is now the International Roadmap for Devices & Systems (IRDS), which will focus on 3DIC infrastructure challenges.

 

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